A 48-dB DR 80-MHz BW 8.88-GS/s bandpass ΔΣ ADC for RF digitization with integrated PLL and polyphase decimation filter in 40nm CMOS

A 2.22GHz 4
^th
-order BP ΔΣ ADC has been realized in 40nm CMOS. The test chip contains a complete system consisting of the ADC core, the PLL with clock generation network, and the digital decimation filters and downconversion (DFD). The quantizers are 6 times interleaved enabling a polyphase structure for the DFD and relaxing speed requirements. Sampled at 8.88GS/s the ADC achieves a DR of 48dB in a band of 80MHz with an IIP3 of +1dBm.