A 2.37Gb/s 284.8mW rate-compatible (491,3,6) LDPC-CC decoder

In this paper, a (491, 3, 6) time-varying LDPC-CC decoder chip supporting five code-rates is implemented in 90nm CMOS technology. The decoder containing 5 processors occupies 2.24 mm² and provides twice faster decoding convergence speed. Maximum throughput 2.37 Gb/s is measured under 1.2 V supply with a 0.024 nJ/bit/proc energy efficiency.