Circuit techniques to improve disturb and write margin degraded by MOSFET variability in high-density SRAM cells

Device variability caused by continued technology scaling makes degradation of disturb and write margin a serious problem for SRAM cells. This paper reports the circuit techniques to cope with it, focusing on two topics: (1) Level Programmable Wordline Driver (LPWD) with Dynamic Array Supply Control (DASC) and (2) Constant-Negative Level Write Buffer (CNL-WB).