High effective-resolution built-in jitter characterization with quantization noise shaping

A novel built-in jitter characterization architecture combining quantization noise shaping and a partial Vernier delay structure is proposed for high resolution jitter measurement. The effective resolution is optimized at the system level as well as the circuit level. Using 90nm CMOS technology, an area of 0.008mm² is occupied. The power consumption is 1.85mW. An effective resolution of 1.5ps is achieved.