An 8Gsps, 65nm CMOS wideband track-and-hold

A track-and-hold (T&H) circuit has been designed and fabricated using the 65 nm CMOS technology from STMicroelectronics. A fully differential architecture has been adopted. The circuit exhibits a -3 dB input bandwidth wider than 8 GHz. At 8 GHz, the maximum sampling frequency, the measured overall power consumption and gain are 178 mW and 0 dB, respectively. The T&H core dissipates around 40 mW. The measured total harmonic distortion (THD) at Nyquist sampling conditions is about -37 dB. The circuit die area is 1.1 mm
²
.