A Low-Flicker Noise Gate-Controlled Lateral–Vertical Bipolar Junction Transistor Array With 55-nm CMOS Technology

The low-flicker noise (
$\hbox{1}/f$
noise) gate-controlled lateral–vertical bipolar junction transistor array (GC-LV-BJTA) is developed with a foundry's 55-nm CMOS technology for low-noise and low-power RF circuit applications. The GC-LV-BJTA is formed by paralleling some unit cells into an array structure for sharing adjacent collectors and bases, thus minimizing the total area. Many efforts, including the use of a deep n-well, a novel layout, an optimized emitter perimeter/area ratio, and a negatively biased gate, have been implemented to suppress the noise level and enhance the current gain. As a result, the GC-LV-BJTA, consisting of 16 unit cells with a 0.16-
$\mu\hbox{m}$
gate length, achieves a high gain of 85.7 with available low
$ \hbox{1}/f$
noise level, as compared with the nMOS or SiGe HBT.