Low cost wafer level parallel test strategy for reliability assessments in sub-32nm technology nodes

The development of new technology nodes has seen an increase of the needs in terms of test capabilities. Because of reliability margins reduction and apparition of specific issues for Time Dependent Dielectric Breakdown or Hot Carrier Injection assessments, large sampling and long time stress at wafer level are indeed more and more often required. In this context, this paper presents the parallel testing strategy we led with the view to facing the growing requirement for reliability tests. It has consisted in the setting up of a home-made parallel test system which, combined with the integration of dedicated test structures for parallel stress and characterization purposes, allows dividing the test time by a factor up to 20 with only minor investments.