Efficient reconfigurable architectures of generic cyclic convolution

This paper presents the design and implementation of a generic cyclic convolution architecture for imaging applications on field programmable gate array (FPGA). Two main architectures are implemented. A parallel architecture using distributed arithmetic (DA) and a sequential implementation using FPGA digital signal processor (DSP) resources were implemented using VHSIC hardware description language (VHDL) and synthesised on Xilinx Virtex-5 FPGA. Experimental results, comparisons and performance analysis of the area, power consumption, maximum frequency and throughput are analysed in this paper. Also a performance comparison between a software implementation and the FPGA implementation has been done. Finally, an evaluation of the generic cyclic convolution has been carried out and reveals a significant trade-off of throughput and maximum frequency.