A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS

A pseudo segmented twofold time-interleaved 6-bit digital-to-analog converter (DAC) occupies 0.28 mm
²
chip area in a standard 90 nm CMOS technology. The DAC enables sampling rates up to 28 GS/s with a power consumption of 2.25 W at a −2.5 V power supply. The output bandwidth is at least 14 GHz. The integral non-linearity (INL) and the differential non-linearity (DNL) are 0.8 LSB and 1 LSB respectively. The estimated effective number of bit (ENOB) at 25 GS/s are 5.5-bit at DC and 4.6-bit at the Nyquist frequency.