Accurate vulnerability estimation for cache hierarchy

Soft errors caused by energetic particle strikes in on-chip cache memories have become a critical challenge for microprocessor design. Architectural Vulnerability Factor (AVF), which is defined as the probability that a transient fault in the structure would result in a visible error in the final output of a program, has been widely employed for accurate soft error rate estimation. In this paper, we propose an improved AVF estimation method. Using the improved AVF computing method, we estimate the reliability of structures in the cache hierarchy (i.e., L1I, L1D, L2 caches). Experimental results show that L1I is the most reliable component, while L2 cache is the most vulnerable component in the cache hierarchy. L2 cache is demonstrated to be almost 23 times more susceptive than L1I. We also investigate the effects of L1D cache organization on the reliability of L1D and L2 caches. Experimental results show that a larger L1D cache is more vulnerable to soft errors, yet brings an improvement of L2 cache reliability. Besides, we find that increasing cache associativity of L1D cache is of little benefit to improve the reliability of cache hierarchy. Based on the quantitative analysis of reliability of structures in the cache hierarchy, we choose different levels of protection for caches, thus maintaining the reliability goal with minimum costs.