A novel area-throughput optimized architecture for the AES algorithm

In this paper, an efficient method for high speed hardware implementation of AES algorithm is presented. So far, many implementations of AES have been proposed, for various goals that effect the SubByte transformation in various ways. These methods of implementation are based on combinational logic and are done in polynomial bases. In the proposed architecture, it is done by using composite field arithmetic in normal bases. In addition, efficient key expansion architecture suitable for 6 subpipelined round units is also presented. By using the proposed architecture in non-feedback mode, a fully subpipelined encryptor with 6 substages in each round unit can achieve a throughput of 43.71 Gbps on a Xilinx XC2VP20-7fg676 device, which is the fastest compared to previous FPGA implementations known to date. The efficiency in terms of equivalent throughput/slice is improved by a factor of 143%. Also in this design, key variation during the encryption operation is supported and it doesn't have any effect on continued throughput of the encryptor.