A10-bit, 20-MS/s, fully differential single transfer phase CBSC pipelined ADC in 0.18µm CMOS

In this paper a fully differential single transfer phase comparator-based switched-capacitor (CBSC) pipelined ADC is presented. The given circuit is a combination of differential and pseudo-differential techniques, so we could benefit from properties of both. Thus, two comparators have been used in the given gain stage, while the output part is fully differential. The obtained combination aims at removal of primary overshoot, omitting two fine current sources, simpler state logic units along with the properties of a fully differential circuit. In terms of power, this architecture consumes much less power than conventional CBSC technique. In order to obtain an appropriate accuracy, a circuit has been introduced to adjust the comparison levels. Finally we designed a 10-bit, 20MS/s fully differential single transfer phase CBSC pipelined ADC in a 0.18-µm 1P6M standard CMOS process. It achieves 79.2-dB spurious-free-dynamic range (SFDR) and 59.74-dB signal-to-noise-and-distortion (SNDR). In addition it consumes 2.25 mW from a 1.8-V power supply at 20MS/s, which obtains a figure of merit of 152 fJ/step.