Accurate Constraints Aware Mapping on Coarse-Grained Reconfigurable Architecture

The rapid diversification and evolution of wireless and multimedia standards change the flexibility of embedded processors from an option to the must. Coarse-Grained Reconfigurable Architectures (CGRAs) which make a good trade off between low power, non-programmable ASICs and high power, flexible DSPs become more and more popular. The mapping of the applications to CGRAs is the key to get high computational throughput. Because there is huge design space to explore on CGRAs, compilers must not only map the programs with high effectiveness, but also with high efficiency. However, there are many sorts of constraints exist during the mapping. Over or under estimate those constraints will lead to either low schedule quality or low efficiency. To meet this challenge, we propose an accurate constraints aware modulo scheduling approach: based on the co-analysis of the architecture and application, the compiler starts the scheduling with enough critical resources reserved and strictly make the re-try follow the correct order. The experiments on wireless base band programs show that the compilation can be speeded up by 300%.