VHDL implementation of high performance RC6 algorithm using ancient Indian vedic mathematics

RC6 is the successor to RC5. It is one of the most promising algorithms that is both fast and secure. It uses four w-bit registers, integer multiplication, quadratic equation and fixed bit shifting. This paper examines how the Vedic algorithm of Urdhva tiryagbhyam speeds up the computation of this algorithm when compared with conventional algorithms in existence.