A 145µW 8×8 parallel multiplier based on optimized bypassing architecture

A low-power parallel multiplier based on optimized bypassing architecture (OBA) is proposed. The proposed OBA has two kinds of adder cells to reduce power consumption by 15.7 %. One is the two-dimensional bypassing adder (TDBA) which performs both row and column bypassing scheme simultaneously, and the other is the modified row-bypassing adder (MRBA) for the proposed row-bypassing scheme. In the proposed TDBA and MRBA, the logic evaluation is partially activated by internal tri-state buffers (ITBs) in order to save the switching power dissipation up to 33.7 % and 32.0 %, respectively. Implemented in 0.13 μm CMOS process, the proposed 8x8 parallel multiplier consumes only 145 μW.