A 1-Mbit CMOS EPROM with enhanced verification

A high-speed 1-Mb EPROM (erasable programmable read-only memory) with an enhanced verify mode to insure adequate threshold shift after programming has been developed. The sense circuitry uses an offset current to shift the sense point to require higher threshold shift during verification. The access time is improved by a clocking scheme that balances the sensing circuitry between column accesses and by a chip architecture optimized for speed. The chip features an access time of 70 ns and an active current of 20 mA. A typical programming time of 50 mu s has been measured. The device is processed in a 1- mu m L/sub eff/ CMOS process with silicides.<
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