A 7.5-ns 32 K*8 CMOS SRAM

A 256 K (32 K*8) CMOS static RAM (SRAM) which achieves an access time of 7.5 ns and 50-mA active current at 50-MHz operation is described. A 32-block architecture is used to achieve high-speed access and low power dissipation. To achieve faster access time, a double-activated-pulse circuit which generates the word-line-enable pulse and the sense-amplifier-enable pulse has been developed. The data-output reset circuit reduces the transition time and the noise generated by the output buffer. A self-aligned contact technology reduces the diffused region capacitance. This RAM has been fabricated in a twin-tub CMOS 0.8- mu m technology with double-level polysilicon (the first level is polycide) and double-level metal. The memory cell size is 6.0*11.0 mu m/sup 2/ and the chip size is 4.38*9.47 mm/sup 2/.<
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