Circuit reliability of hot electron induced degradation in high speed CMOS SRAM

The access time degradation of a high-speed 256K CMOS SRAM (static random-access memory) is measured after high voltage stress. The circuit performance degradation due to hot electron effects is measured using BERT (Berkeley Reliability Tool), a circuit reliability simulator. Propagation delay between internal nodes is experimentally measured to verify the simulated result. No degradation is observed after a V/sub c//sub c/ = 6.5 V burn-in. This is in agreement with the simulated result. Simulation predicts that access time degradation in the 256 K SRAM (after 10 years product lifetime at V/sub c//sub c/ = 5.5 V) is 0.44 ns in the present 0.8 /spl mu/m technology. A similar analysis on the next 0.5 /spl mu/m generation of technology estimates an access time degradation of 1.45 ns.