A new design for testability method: Clock line control design

Clock line control (CLC) is proposed as a new design for testability (DT) technique which can transform a complex test generation problem into many small ones that are efficiently manageable by selectively clocking modules. Hardware overhead in CLC increases in proportion to the number of sequential modules rather than individual memory elements, which result in very low overhead. The sequential modules become combinational when their clocks are disabled, and they are efficiently handled by the test generator. Test generation proceeds by expanding multiple time frames for one sequential module at a time. The total number of states the test generator considers at one time is determined by the number of state variables in the clocked module instead of the entire circuit.