0.5 /spl mu/m 1 M gate CMOS SOG

A one-million-gate CMOS SOG (sea-of-gates) array has been developed by using half-micron three-layer metal CMOS technology. The high speed I/O (input/output) buffers, RAM cell libraries, and clock skew management make it possible to achieve over 100 MHz operating at 3.3 V. A gate density of 4.7 kG/mm/sup 2/ and a bit density of 1.8 kbit/mm/sup 2/ for asynchronous dual-port RAMs are obtained. The GTL (Gunning transceiver logic) interface cells are prepared in the I/O buffer cell library. The clock skew is less than 500 ps under 5000 flip-flops at 100 MHz on the chip.