A programmable clock generator with 50 to 350 MHz lock range for video signal processors

Using 0.5-/spl mu/m CMOS triple-layer Al technology, a programmable clock generator based on a PLL (phase-locked loop) circuit has been developed for use as an on-chip clock generator in a 300-MHz video signal processor. It generates an internal clock whose frequency is an integral multiple of an external clock frequency, and its oscillating frequency ranges from 50 to 350 MHz. Experimental results show that the clock generator generates a 297-MHz clock with jitter reduced to 180 ps with a 27-MHz input clock, and that it oscillates at up to 348 MHz with a 31.7-MHz input clock.