Design and characterization of SiGe TFT devices and process using Stanford's test chip design environment

Stanford's test chip environment has been used to rapidly prototype a SiGe TFT process. The environment selected test structures tailored for the device/process. Then, with minimal effort and using parameterized test structures, the designer assembled a diagnostic test module. This module was used successfully in the development and optimization of the process, leading to the fabrication or high performance SiGe TFTs.