Reliability and performance optimization of 42V N-channel drift MOS transistor in advanced BCD technology

Optimization flow for a 42V N-channel drift MOS in an advanced BCD technology in terms of performance and stability is described. The origin of the very fast on state resistance (R
_on
) degradation detected during reliability tests under off state on the starting device has been identified in borderless silicon nitride used as stop layer during contact etch. The final solution including a process step introduction, device geometry modification and drain doping profile optimization improves performance and addresses both voltage capability and reliability requirements.