Technology Assessment Methodology for Complementary Logic Applications Based on Energy–Delay Optimization

Historically, the off-state current
I
_off
and the supply voltage
Vdd
are specified as technology targets for Si metal-oxide-semiconductor field-effect transistors (MOSFETs) at each technology node. Emerging device technologies such as III-V transistors, carbon-nanotube FETs (CNFETs), and tunneling FETs (TFETs) are often targeted to outperform Si MOSFETs at the same
I
_off
and
Vdd
values. However, the conclusions from the conventional methodology are limited for advanced technology and diversified applications, when Dennard scaling is inefficient and different device structures are invented. We present a new device-technology assessment methodology based on energy-delay optimization, which takes into consideration key circuit-level information, such as logic depth, activity factors, and fanout (FO). Our methodology starts from device
I
-
V
and
C
-
V
characteristics and treat
I
_off
and
Vdd
as “free variables.” Together with device and supply-voltage variations, we obtain a corresponding and different optimal set of
I
_off
and
Vdd
and optimal energy-delay for each emerging device. We show that today's best available III-V transistors and CNFETs can outperform the best Si FETs by 1.5-2 and 2-3.5 times in terms of energy efficiency, respectively. Projected into the 10-nm-gate-length regime, III-V-on-insulator, CNFETs, and TFETs are 1.25, 2-3, and 5-10 times better than the International Technology Roadmap for Semiconductors target, for FO1 delays of 0.3, 0.1, and 1 ns, respectively.