Effect of junction engineering for 38nm BE-SONOS charge-trapping

As NAND Flash device scales down, the source/drain junction engineering becomes a key factor for improving the short-channel effect, self-boostiSg program inhibit window, and cell reliability. In this work, the impact of trap-layer above junction (cut-ONO or non-cut ONO), Source/Drain Si recess, and junction doping are studied extensively for the 38nm half-pitch BE-SONOS charge-trapping NAND Flash devices. Our results suggest that a non-cut ONO with junction-free device shows the best memory window and small endurance degradation