Manufacturing advantages of single wafer high current ion implantation

Since the advent of the self aligned gate process for fabrication of MOS devices, ion implantation has been used to dope source and drain structures. High throughputs required for volume manufacturing dictated a batch process equipment architecture that solved two fundamental problems: (1) the inability to develop high current ion optics suitable for single wafer processing, and (2) the inability to solve problems associated with wafer heating and photo-resist processing. Recent advances in ion optics technology and heat removal (wafer cooling), as well as the downward trend in junction depths for advanced CMOS devices have solved both problems. Single wafer high current ion implantation of 200 and 300 mm diameter wafers offers significant advantages over batch implantation for both process engineering and manufacturing. This paper reviews manufacturing advantages including reduced scrap, higher throughput, smaller system footprint and reduced operating costs with respect to factory automation. We present a single wafer end station with throughputs in excess of 200 wafers per hour. The end station utilizes two independent vacuum load locks. Wafers are processed from a cassette in one load lock while vent, pump and cassette exchange occur in the other. Wafers are transported horizontally, in vacuum at accelerations of less than 0.1 g. The system can be optimized to obtain approximately 50% beam on wafer time resulting in throughputs in excess of 170 wafers per hour for source and drain doses PI modest (15 mA) beam currents.