Characterization of surface barrier effects from Cu-implanted SiO/sub 2//Si interfaces

The effects of Cu in silicon as a contaminant ion have been studied by many groups. As a result its effect on gate oxide integrity through surface defect decoration and retardation of thermal oxide growth have become recognized problems for VLSI and ULSI. However its effects on surface charge, barrier height, and minority carrier generation are now as well-understood since the ability to study Cu-induced surface defects directly from surface cleans or implant processing is reduced by the addition of other contaminant species or the compromising effects from additional process steps required to fabricate C-V test capacitors, In this study we address this problem by using a frequency-swept, high-injection surface photovoltage method which follows the direct, ex-situ examination of the surface barrier condition and interfacial states affecting generation lifetime. For this investigation we have generated a variety of Cu-contaminated samples fabricated by ion implantation over three oxide thicknesses and two Cu surface concentrations. These are compared to samples with Cu introduced by buffered-oxide-etch (BOE) and electrical results from standard C-V tests. By using passive optical probes, we present direct observation of surface state conditions due to the presence of Cu.