Low dose ion implantation characterization for Vt control

Tight control of threshold voltages (Vt's) is required for DRAM, logic and analog designs. Process factors such as oxide thickness, implantation dose/energy, and substrate doping are critical to meet the product Vt targets and tolerances. The peak carrier densities of threshold voltage adjust implants used in DRAMs are located very close to the Si-SiO2 interface, In this paper, we apply an implant dose monitoring technique using Hg-gate MOS pulsed CV for optimization of low doses for control Vt's for N- and buried channel PFETs in quarter micron technology. This monitoring technique called Partial Implant Dose (PID) essentially measures a portion of the total implanted dose obtained by integrating the carrier concentration profile between two defined limits. PID measurements have been successfully applied to identify ion implanter tool problems. Tool stability, dose offsets and uniformity of different implanters were controlled by mapping PIDs for 200 mm wafers in a semi-manufacturing fab. Implant energies of 10-60 keV with a dose range of 1E12 to 7E12/cm/sup 2/ were used through 7.5 to 15 nm screen oxides. Furnace and RTA activations were examined. Al-gate MOS capacitors fabricated by evaporation of Al-dots through a shadow mask were used for comparison with Hg-gate PID measurements. The Hg-gate measurements predict that a 5% variation in nominal implanted dose correlates with a 5% variation in PIDs, Day to day dose repeatability for B+ 10 keV 5.5E12/cm/sup 2/ is about 1%. The in-line PID measurements are correlated with device Vt's.