A 350 MHz 3.3 V 4 Mb SRAM fabricated in a 0.3 /spl mu/m CMOS process

A 35OMHz 4Mb SRAM chip in 2.5V 0.3/spl mu/m CMOS achieves a 4.1 ns flow-through access and uses self-timed, self-resetting, and low-signal swing circuits. The SRAM interfaces to LVTTL levels with a PECL clock, or to HSTL levels with either a single-ended or differential clock. The chip can be packaged in either 128k/spl times/36 or 256k/spl times/18 organizations and supports pipeline, dual-clock flowthrough, or register-latch timing protocols. A voltage regulator drives the internal power grid. High-speed circuits are used for the critical read performance path, and low-power static circuits are used in paths that do not gate chip performance.