A 12 b 28-channel trimless DAC

In ATE systems, the electronics for each pin employs more than ten 12 b DACs to provide dc level settings (i.e. pin driver rails, window comparator thresholds, programmable load currents, etc.). With increasing pin counts, a multi-channel chip structure becomes inevitable. A 12.7 b trimless DAC suitable for multi-channel applications is fabricated in a conventional double-metal 1.0 /spl mu/m CMOS process. The chip contains 28-channel DACs in 8.25/spl times/8.8mm/sup 2/ and consumes about 110 mW. The DAC utilizes a triple-rank architecture and binary-weighted transconductance (gm) to eliminate trimming and calibration.