A 4.25 GHz BiCMOS clock recovery circuit with an AV-DSPD architecture for NRZ data stream

Demand for high-speed serial data communication systems is increasing for computer data links using the 4.25Gb/s ANSI fiber-channel standard. A clock-recovery circuit (CRC) that extracts a clock signal from the transmitted data stream is essential for these systems. An AV-DSPD architecture operates at a frequency two times higher than that of an internal phase detector that limits the conventional CRC frequency. A CRC VCO is controlled by the absolute value of divided signal phase differences (AV-DSPD). Based on the AV-DSPD architecture, a 4.25GHz CRC is suitable for non return to zero (NRZ) data streams. Although the CRC consists of bipolar transistors, fabrication is in 0.251/spl mu/m BiCMOS allowing the CRC to be integrated with other digital blocks, such as a byte-lock detector, necessary for data link systems using the fiber-channel standard.