Development of single-chip multi-GB/s DRAMs

Discusses improvement of current device jitter budget. A DRAM incorporating these improvements is expected to operate with 1.3Gb/s/pin signaling rate (650MHz clock rate) delivering 5.2GB/s from a 32b interface. Such a 64Mb density DRAM will exhibit a fill rate of 650times/s. Compared to an industry-standard 64M SDRAM operating at 66MHz with its 33times/s fill rate in a 2Mx32 organization, the ratio is 19.7:1.