A 300 MHz CMOS microprocessor with multi-media technology

This 7.5M transistor CMOS microprocessor is architecturally equivalent to, and the next generation superset of, a previous microprocessor with dynamic execution (Colwell and Steek, 1995). It implements Intel MMX/sup TM/ Technology instructions to enhance performance of media and communication applications. It doubles the on-chip instruction and data caches of the previous generation processor to 16 kB each and implements a dedicated bus to access large off-chip second-level caches. This processor also implements renaming of data segment registers. These and other features result in projected performance of /spl sim/ 12.0 Specint95 for this 300 MHz processor and 3-12/spl times/ performance improvement for kernels of multimedia and communication applications (for example DSP, video and voice) over a scalar implementation. It is the highest performance Intel-Architecture compatible microprocessor.