A 1.2 V to 3.3 V wide-voltage-range DRAM with 0.8 V array operation

DRAM arrays operating with power supply below 1 V, with stable sensing and high speed are required for multi-media systems. Reduction of data-retention current is also important. The authors present two data-retention current reduction techniques: charge-transfer pre-sensing scheme (CTPS) with 1/2Vcc bit-line precharge; and non-reset row block control (NRBC). An experimental 32 Mb DRAM using these techniques is fabricated in a 0.25 /spl mu/m triple-well CMOS technology.