CMOS hot-carrier degradation and device lifetime at cryogenic temperatures

Cryogenic operation of CMOS circuits is of interest due to potential improvements in performance. However, low temperature operation exacerbates hot-carrier effects in CMOS transistors. Currently, there exists a controversy in the literature on the issue of the worst-case gate voltage stress condition at low temperatures. This work explains the apparent contradiction in the literature. Specifically, we show that at low temperature the worst-case hot-carrier lifetime is a function of the channel length and drain bias. These findings are important in providing insight to optimizing device design for low temperature operation and for understanding and developing a correct lifetime extraction methodology at cryogenic temperatures.