Hole trapping as the rate-limiting factor in LDD nMOSFET degradation

We have observed a unique phenomenon during low-gate voltage (V/sub G/) static stressing of a CMOS circuit, that was designed for dynamic stressing. Static stressing was performed by probing 0.44 /spl mu/m lightly-doped-drain (LDD) nMOSFET devices that were discrete (isolated), as well as devices that were part of a circuit which consisted of a 301-stage BiCMOS ring-oscillator, followed by a chain of 6 inverters. Although the measured substrate currents (I/sub SUB/) for the circuit and discrete devices were quite similar, significantly more hole trapping was observed under low-V/sub G/ static stressing of circuit devices. It is clear that the extent of hole trapping is circuit dependent, and that in actual operation the devices would never undergo such static stressing. We focused our efforts on understanding the mechanisms of interface-state formation. Charge pumping (CP) measurements were used to confirm hole trapping and subsequent interface-state formation after each stress interval. The results were examined with the aid of the model proposed by Lai (1983), which states that interface state formation requires hole trapping followed by electron trapping. It was found that while both electrons and holes are needed for the formation of interface states, it is hole trapping that is the rate-limiting factor in device degradation.