Integrated micromachined decoupled CMOS chip on chip

A novel technology for the fabrication of thermally, electrically, and mechanically decoupled n-doped silicon microstructures is presented. The n-silicon may contain p-well regions and, therefore, unrestricted CMOS circuitry and transducers. Furthermore, the technology enables the inexpensive fabrication of silicon membranes with different thicknesses without using epi-layer wafers. It is based on a commercially available industrial CMOS multi-well process which is followed by an anisotropic KOH etching step from the wafer backside using an electrochemical etch stop. As an example, a decoupled CMOS magnetic sensor microsystem in a deep n-well was realized. The well is suspended by a dielectric membrane. The thermal isolation of the suspension has a thermal resistance of 4600/spl deg/C/W. The microsystem has a thermal time constant of 3.3 ms. The stabilization of the sensor operation temperature reduces drift effects of the sensor signal offsets related to ambient temperature changes by a factor of 5.