Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC

There are one PTLSCR and one NTLSCR devices in parallel with output PMOS and NMOS devices, respectively, to improve ESD robustness of CMOS output buffer in deep submicron CMOS IC's. PTLSCR (NTLSCR) is merged together with output PMOS (NMOS) device to save layout area for high-density applications. Experimental results show that this proposed CMOS output buffer can sustain up to 4000 V (700 V) Human-Body-Mode (Machine-Mode) ESD stresses with small layout area in a 0.6-/spl mu/m CMOS technology with LDD and polycide processes.