Variation-tolerant design of D-flipflops

This paper discusses vulnerability of a D-flipflop (D-FF) under within-die (WID) variation. The effect of WID variability on D-FF timing characteristics is examined and it is revealed that the setup time of a D-FF becomes larger than that of the worst corner condition. In order to suppress this “worse-than-the-worst-corner” behavior, variation-tolerant D-FFs are proposed and verified in a 65nm process, including a D-FF with over-sized clock drivers which reduces performance variability by 29% at 1.2V and 55% at 0.7V with power overhead of 14%.