Asymmetrical ground gating for low leakage and data robust sleep mode in memory banks

A new asymmetrical ground gated 7T SRAM circuit technique is presented in this paper to lower leakage currents and enhance noise immunity in idle memory banks. A novel write assist scheme is proposed to enhance write margin with the new memory circuit. The leakage power consumption is suppressed by up to 4.30× and the data stability is enhanced by up to 4.79× as compared with the previously published ground gated SRAM circuits in a UMC 80 nm CMOS technology. Furthermore, the write margin is increased by up to 59.94% with the new asymmetrical memory circuit as compared to a previously published asymmetrical SRAM ground gating technique.