Reliable and cost effective anti-collision technique for RFID UHF tag

This paper presents a proposed Reliable and Cost Effective Anti-collision technique (RCEAT) for Radio Frequency Identification (RFID) Class 0 UHF tag. The RCEAT architecture consists of two main subsystems; PreRCEAT and PostRCEAT. The PreRCEAT subsystem is to detect any error in the incoming messages. Then the identification bit (ID) of the no error packet will be fed to the next subsystem. The PostRCEAT subsystem is to identify the tag by using the proposed Fast-search Lookup Table. The proposed system is designed using Verilog HDL. The system is simulated using Modelsim and synthesized using Xilinix Synthesis Technology. The system has been successfully implemented in hardware using Field Programmable Grid Array (FPGA) Virtex II. The output waveforms from the FPGA have been tested on the Tektronix Logic Analyzer for real time verification. Finally the RCEAT architecture is resynthesized using Application Specific Integrated Circuit (ASIC) technology for on-chip implementation. This technology consists of 0.18 μm Library, Synopsys Compiler and tools. From the hardware verification results, it shows that the proposed RCEAT system enables to identify the tags without error at the maximum operating frequency of 180MHz. The system consumes 7.578 mW powers, occupies 6,041 gates and 0.0375 mm
²
area with Data arrival time of 2.31 ns.