A multiphase all-digital delay-locked loop with reuse SAR

A multiphase all-digital delay-locked loop (DLL) with reuse SAR has been designed with TSMC 0.18μm CMOS technology. The proposed reuse successive approximation register (Reuse SAR) reduces the hardware cost effectively as compared with a conventional SAR or a two-stage SAR. The digital to voltage convertor has six coarse controlled bits and six fine controlled bits to adjust voltage for voltage controlled delay line. The core area is 206.8 μm × 217.4 μm and power consumption is 22.6 mW at 125 MHz.