Design and analysis of the Current Reuse Technique and Folded Cascode Power Constrained Simultaneous Noise and Input Matching LNAs with distributed and lumped parasitic

Two LNA topologies were implemented to study on the performance of the post-layout simulation with lumped and distributed parasitic. The performance of the post-layout simulation with different types of parasitic is benchmarked against the measurement results for both topologies previously designed using the post-layout simulation with lumped parasitic. The LNA topologies are the Current Reuse Technique (CRT) Power Constrained Simultaneous Noise and Input Matching (PCSNIM) and the Folded Cascode (FC) PCSNIM. These designs were implemented on Silterra's 0.18μm CMOS process. It is found that the post-layout simulations with distributed parasitic better resemble the measurement results. Based on this finding, the optimization of the CRT and FC PCSNIM LNAs were performed. The S₁₁, S₂₁ and S₂₂ are -14.48dB, 17.44dB and -18.48dB, respectively, for the CRT and -20.52dB, 16.39dB and -22.88dB, respectively, for the FC. The results show that both LNAs are able to comply to the requirements of the WCDMA application.