Phase Noise Issues With FPGA-Embedded DLLs and PLLs in HEP Applications

Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) are available as embedded hard-macros in the latest Field Programmable Gate Arrays (FPGAs). Their main features are clock phase de-skewing, frequency multiplication and division. Moreover, the availability of PLLs allows the user to perform jitter filtering too. The clock signal at the output of a DLL or a PLL has a phase noise, which has to be taken into account in timing sensitive applications, such as analog-to-digital conversion, time measurements or high-speed serial links.