Optimization of pseudo-boolean satisfiability algorithm for FPGA routing

In order to improve the negative effect of increasing transformation cost of pseudo-Boolean Satisfiability algorithm in the routing process, a new routing algorithm was proposed for FPGA, which combined advantages of pseudo-Boolean Satisfiability and geometric routing algorithm. In the routing process, one of geometric routing algorithm-PathFinder was chosen firstly for FPGA routing. If not successful, then use pseudo-Boolean Satisfiability algorithm. Moreover, technique of static symmetry-breaking was added to carry out pretreatment of pseudo-Boolean constraints, detecting and breaking the symmetries in the routing flow. The purpose was to prune search path, and the cost was consequently reduced. Preliminary experiments results show that the hybrid approach can reduce the runtime observably, speed up the solving process, and have no adverse affect on overall program.