A programmable demodulator for oversampled analog-to-digital modulators

A programmable DSP (digital signal processor) architecture for use in an oversampled A/D (analog-to-digital) converter system is introduced. Based on this architecture, a set of synchronization equations for configuring the entire oversampled system for arbitrary speed-accuracy specifications is presented. The generality and simplicity of the architecture allow the reduction of this procedure to running high-level, user-friendly software and programming PROMs (programmable read-only memories). The architecture was implemented in a 2.0- mu m N-well CMOS technology. Fabricated samples demonstrated the ability to handle many applications, including 16 b of SNR (signal-to-noise ratio) for the digital audio (20-kHz baseband) and 18 b of SNR for voiceband (4-kHz baseband). It is concluded that this DSP architecture is the most general and efficient computation engine for FIR/IIR (finite impulse response/infinite impulse response) filtering of 1-b signals. It is capable of over 30 MIPs. The architecture's simplicity and flexibility facilitate its interfacing with a high-level, user-friendly software package.<
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