Rapid Prototyping of an Automated Test Harness for Forward Error Correcting Codes

This paper presents a design flow for the rapid prototyping of forward error correction (FEC) systems in the Xilinx System Generator tool. In this instance two FEC systems were tested, both Turbo codecs. One was designed to comply with the UMTS standard, the other was designed to comply with the cdma2000 standard. The target hardware for this system is a Field Programmable Gate Array (FPGA). The System Generator tool and the cdma2000 Turbo code standard are discussed. A description of the implemented test harness is given along with simulation results and a comparison of simulation times for both hardware and software implementations of the system. Results presented show performance differences between UMTS and cdma2000 codecs. It is also shown how fast termination affects decoder performance.