Scalable Architectures for 100 GbE Packet Processing

This paper addresses the question, how device technologies and architectures scale towards 100G packet processing. The evolution of field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) technology is analyzed in terms of throughput, interfaces, density, and power. Moreover, the 100 Gigabit Ethernet (100 GbE) component ecosystem is subject of a detailed review regarding functional split and interfaces. Domains are identified that cannot keep up with the increased throughput demand, and therefore limit higher integration. It is concluded that device technology has to improve significantly in the strive for economical and energy-efficient 100 GbE networking. In the meantime, techniques such as caching, pipelining, and load balancing open viable paths towards 100 GbE packet processing.