A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining

In this paper, the authors also show how clocking overhead can be reduced through circuit techniques to facilitate super pipelining while process variation is addressed through the use of latch-based design. Additionally, architecture modifications are proposed to improve energy efficiency and throughput. Measurements show that the FFT core consumes 17.7nJ per 1024-pt complex FFT while operating at 30MHz at V
_dd
=0.27V, demonstrating an improvement over the FFT energy efficiency.