Thin-BOX Poly-Si Thin-Film Transistors for CMOS-Compatible Analog Operations

This paper presents device models and optimization methodology for reducing short-channel effects in low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs), which are suitable for standard complementary metal-oxide-semiconductor (CMOS)-compatible analog operations. We analyze channel-length modulation to determine appropriate channel length having a single grain boundary in the channel fabricated using excimer laser-annealed crystallization under low-temperature constraint. Furthermore, buried-oxide-induced barrier lowering (BIBL) is investigated in poly-Si TFTs. BIBL makes the effective channel length shorter, resulting in difficulty to use LTPS TFTs for analog applications due to small output resistance r
_out
. We show that, with scaling of the buried-oxide (BOX) thickness T
_box
and an appropriate channel length, r
_out
and the normalized transconductance g
_m
/I
_d
(with T
_box
= 10 nm) can be improved by 103% and 8%, respectively, compared with thicker BOX (T
_box
= 50 nm). In addition, due to the decrease in leakage currents, the I
_on
/I
_off
ratio of the thin-BOX device can be three times larger than that of the thicker BOX device. Based on the process-constrained optimized device, we designed a 417-μW 65-dB folded-cascode operational amplifier with 2-V supply for CMOS-compatible operations.